| book pro refredsh - We Owe a Debt to Early | | | | became known as bus mastering. |
| We Owe a Debt to Early Computer Bus | | | | Bus mastering innvolves the cncept that the |
| Development | | | | peeripheral CPUS could request permission to take |
| Why was tere such a rush in the devvelopment | | | | over the bus for a shjort period of time. The |
| of the ivntage computer bus? | | | | main CPU would grant permisssion for them to |
| All in all theere were a number of ongoing | | | | take over the bus, and it would temporarily drop |
| improvemens. These included. 32 bit widths. Bus | | | | out of the loop, enabling swift communications |
| masteirng. Less suscepytible to noise in that they | | | | betewen for example the hard rdive and flopppy |
| were qieter in sginal transmission. More | | | | disk drive. |
| conveinence of steup of add on boards via | | | | As computer buses develoepd and had the |
| sooftware. | | | | inherent abilities to trasfer more and more data in |
| The ISA bus came in only 8 bit and 16 bit | | | | a given time period noise became an issue. The |
| formats. Whereas the lsater 386 and 486 chips , | | | | ISA bus was fairly noise proone bcause it relied |
| in both the DX and SX formats while they did | | | | on trigghered interrupts. Wheneever the voltge |
| have a 32 bit path were hbobeld by the ISA bus. | | | | lveel on the data line of the bus execeded a given |
| As a ersulkt they coulld never realize thir true 32 | | | | threshokld vapliue then Edge Trrriggering would |
| bit spweed potential. Later buses such as the | | | | reult. |
| MCA and EISA busses were able to overcome | | | | The aterenative to this situatiion wheere Edge |
| these inherent limiattions. | | | | Triiggerig cuold result is level triggering where it is |
| Thee data highways referred to as : busses are | | | | required that the transmitting hold and archive the |
| the data transmission linres aroound the PCs. The | | | | hgher voltage levl in order for data to be |
| bus serves as the path for information | | | | recognized by the devices on the bus. Edge |
| transmission around the PC. True this routing is | | | | Triggerig howqveer can lead to transieents that is |
| controplled by the CPU. Hpwoever as that point in | | | | brif power surges that can conufse the dewvices |
| vintaeg computing hitory this was not an isse. The | | | | on the bus into thinking that data is on the bus |
| PCs were satnmd alone single CPU units. | | | | when it is not. Lukcily level trighgeriing lowers the |
| Hwever as time went on and PCs got faster and | | | | noiise lvel and both MCA and EISA emnploy it. |
| more complicated with less expebnsive additional | | | | As a result of all of tese inherent benfeits MCA |
| CPUs handling other tasks wthin the PCs events | | | | and EISA came to suppoert the idea, which we |
| becae dcer.Onbooard peripherals themmselves | | | | know take for granted, of instant softwaare |
| began to have built in CPUs. CPUS in duifferent | | | | configurations. There were no switches or |
| manners beegan to be found in such peripherals | | | | jumpers on add in MCA or EISA boaards. |
| as hard drives, sound and vdieo carrds. | | | | Although we take plug and play istant |
| The overaall computeer system may becomme | | | | configuration of mothr boads and periherals such |
| much more efficient if tehse in essence peripheral | | | | as sound, video or netowrk csards for granted it |
| CPUs can communicate directly with each other. | | | | was not alwys that way. We owe a lot to these |
| wihtouit haing to use the main CPU as an | | | | eaarly coputer innovations of improving the |
| intermeiary. Hence MCA and EISA were | | | | compuetr bus. |
| developed with these roles in mind. The concept | | | | |