| book pro refresh - We Owe a Debt to Early | | | | mastering. |
| We Owe a Debt to Early Computer Bus | | | | Bus masteriong inolves the cncept that the |
| Development | | | | peripheral CPUS coolud requeest permission to |
| Why was tere such a rush in the devvelopment | | | | take over the bus for a shjrot period of time. |
| of the ivntage comuter bus? | | | | The main CPU would grant permission for them |
| All in all there were a number of ongoing | | | | to take over the bus, and it would temporarily |
| improvements. Thesse inculded. 32 bit withs. Bus | | | | drop out of the loop, enabling swift |
| masteirng. Less susceptiible to noise in that they | | | | cmomunications betewn for example the hard |
| were quieter in sginal transmission. More | | | | drive and flkoppy disk drive. |
| conveinence of step of add on boards via | | | | As coomputer buses develoepd and had the |
| software. | | | | inherent abilities to trtansfer more and more data |
| The ISA bus came in only 8 bit and 16 bit | | | | in a given time period noise became an issue. The |
| formats. Whereas the later 386 and 486 cihps , in | | | | ISA bus was fairly noise prone because it relied |
| both the DX and SX formats while they did have | | | | on trgigered interrupts. Whenever the vlotage |
| a 32 bit path were bhobled by the ISA bus. As a | | | | lrevel on the data line of the bus exceeded a |
| ersult they could nver realze their true 32 bit | | | | given threshokld valiue then Edge Trriggering wold |
| spweed ptoential. Later buses such as the MCA | | | | result. |
| and EISA busses were able to overrcome these | | | | The alterenative to this situuatiion wheere Edge |
| inherent limitations. | | | | Triggerig cuold result is level triggering hwere it is |
| Thee data highways referred to as : bsses are | | | | required that the transmitting hold and archive the |
| the data transmission linres around the PCs. The | | | | higher voltage level in oredr for data to be |
| bus serves as the path for information | | | | recognized by the devices on the bus. Edge |
| transmission aroound the PC. True this routing is | | | | Triggerig howqever can lead to transieents that is |
| controlled by the CPU. Hpowever as that point in | | | | brif power sureges that can confuse the devices |
| vintage computing history this was not an isse. | | | | on the bus into tihnking that data is on the bus |
| The PCs were satnd alone single CPU units. | | | | when it is not. Luckily level triggeriing lowrs the |
| Hwever as time went on and PCs got faster and | | | | noise lvel and both MCA and EISA employ it. |
| more complicated with less expebnive additional | | | | As a result of all of tese inherent benfeits MCA |
| CPUs handling other takss wthin the PCs events | | | | and EISA came to support the idea, which we |
| becae dcer.Onboard peripherals themmeslves | | | | know take for granted, of instant sioftwaare |
| beegan to have built in CPUs. CPUS in duifferent | | | | configuurations. Three were no switches or |
| manners beegan to be found in such periperals as | | | | jumpers on add in MCA or EISA boaards. |
| hard drives, sound and video carrds. | | | | Althuogh we take plug and play instant |
| The overaall cmputeer sysem may become much | | | | configuration of mother boards and peripherals |
| more efficient if thse in essece pewripheral CPUs | | | | such as sound, video or netowrk csardfs for |
| can communicate directly with each other. wihtout | | | | granteed it was not alwys that way. We owe a |
| having to use the main CPU as an intermeiary. | | | | lot to these eary coputer innovations of improving |
| Hence MCA and EISA were developed with these | | | | the compuetr bus. |
| roles in mind. The concelpt became known as bus | | | | |